In the case of semiconductor memory devices one differentiates between so-called functional memory devices (e.g., PLAs, PALs, etc.), and so-called table memory devices, e.g., ROM devices (ROM=Read Only Memory) and RAM devices (RAM=Random Access Memory or read-write memory, respectively).
A RAM device is a memory for storing data under a predetermined address and for reading out the data under this address again later.
The corresponding address can be input into the RAM device via so-called address pins or address input pins. A plurality of, e.g. 16, so-called data pins or data input/output pins (I/Os or inputs/outputs) are provided for the input and output of the data. By applying an appropriate signal (e.g. a read/write signal) at a write/read select pin it can be selected whether (at the moment) data are to be stored or to be read out. Since as many memory cells as possible are intended to be accommodated in a RAM device, one has been trying to realize same as simple as possible. In the case of so-called SRAMs (SRAM=Static Random Access Memory), the individual memory cells consist e.g. of few, for instance 6, transistors, and in the case of so-called DRAMs (DRAM=Dynamic Random Access Memory) in general only of one single, correspondingly controlled capacitor with the capacitance of which one bit each can be stored as charge. This charge, however, remains for a short time only. Therefore, a so-called “refresh” must be performed regularly, e.g. approximately every 64 ms.
In the case of memory devices, in particular DRAM devices, the individual memory cells are—positioned side by side in a plurality of rows and columns—arranged in a rectangular matrix or a rectangular array for technological reasons.
In order to obtain a correspondingly high total storage capacity and/or to achieve a data read or write rate that is as high as possible, a plurality of, e.g., four—substantially rectangular—individual arrays (so-called “memory banks”) may be provided in one single RAM device or chip (“multi-bank chip”) instead of one single array.
To perform a write or read access, a particular predetermined sequence of instructions has to be run through:
For instance, by means of a word line activate instruction (activate instruction (ACT)) a corresponding word line—that is in particular assigned to a particular individual array (“memory bank”)—(and that is defined by the row address (“row address”) is first of all activated.
Subsequently—by means of a corresponding read or write instruction (RD or WT instruction)—it is initiated that the corresponding data—which are then exactly specified by the corresponding column address—are correspondingly output (or read in).
Next—by means of a word line deactivate instruction (e.g., a precharge instruction (PRE instruction) the corresponding word line is deactivated again, and the corresponding array (“memory bank”) is prepared for the next word line activate instruction (ACT).
In order to ensure a faultless operation of the DRAM device, particular time conditions have to be observed.
A particular time interval tRCD (so-called RAS-CAS delay) must, for instance, lie between the word line activate instruction (ACT instruction) and a corresponding read (or write) instruction (RD (or WT) instruction). The RAS-CAS delay results, for instance, from the time required by the sense amplifiers for amplifying the data supplied by the memory cells addressed by the word line.
Correspondingly, a corresponding time interval tRP (so-called “row precharge time” delay) also must be observed between a word line deactivate instruction (PRE instruction) that follows the read (or write) instruction (RD (or WT) instruction) and a subsequent word line activate instruction (ACT instruction).
By the—above-explained—providing of a plurality of independent arrays (“memory banks”) in one single DRAM device—for which corresponding word line activate and deactivate instructions, etc. are generated by a corresponding memory device controller (“memory controller”) independently of each other—, the delay times that result altogether for the device during the writing or reading of data can be reduced, and thus the performance of the DRAM device can be increased (for instance, since corresponding write or read accesses can be performed in parallel or overlapping in time, respectively, with a plurality of different arrays (“memory banks”)).
In order to further increase the performance of a corresponding DRAM device, the corresponding memory device controller (“memory controller”) may—after the output of a corresponding word line activate instruction (ACT instruction) and of a corresponding read (or write) instruction (RD (or WT) instruction)—leave the respective word line first of all in an activated state (i.e. the corresponding word line deactivate instruction (PRE instruction) may first of all be inhibited).
If then—which is, from a statistic point of view, the case very frequently—in the corresponding array (“memory bank”) (a) memory cell(s) is/are accessed next which is/are assigned to the same word line or row as the memory cell(s) that was/were accessed last, the output of a further word line activate instruction (ACT instruction) can be omitted.
Instead, the memory device controller (“memory controller”) may directly output a corresponding read (or write) instruction (RD (or WT) instruction) to the respective array (“memory bank”) and thus it may be achieved that the corresponding data are read out (or input) instantly—without a corresponding RAS-CAS delay tRCD occurring.
Only if—which is, from a statistic point of view, the case less frequently—in the corresponding array (“memory bank”) (a) memory cell(s) is/are to be accessed next which is/are assigned to a different word line or row than the memory cell(s) which was/were accessed last—, the corresponding—last used—word line is deactivated by the output of a corresponding word line deactivate instruction (PRE instruction), and then the—new—word line is activated (by the output of a corresponding, further word line activate instruction (ACT instruction)).